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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processor adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.3113 ? 2010 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bi t floating-point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memory5 mbits on-chip ram, 4 mbits on-chip rom up to 400 mhz operating frequency code compatible with all other members of the sharc family the adsp-2148x processors are available with unique audio- centric peripherals, such as the digital applications interface, serial ports, precision clock generators, s/pdif transceiver, asynchronous samp le rate converters, input data port, and more for complete ordering information, see ordering guide on page 65 figure 1. function al block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit iod0 32-bit epd bus 64-bit core bus cross bar dai routing/pins s/pdif tx/rx pcg a - d dpi routing/pins spi/b uart block 1 ram/rom block 2 ram block 3 ram ami sdram ctl ep external port pin mux timer 1 - 0 sport 7 - 0 asrc 3 - 0 pwm 3 - 0 dag1/2 core timer pdap/ idp 7 - 0 twi iod0 bus dtcp/ mtm pcg c - d peripheral bus 32-bit core flags/ pwm3 - 1 jtag internal memory dmd 64-bit pmd 64-bit core flags iod1 32-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dpi peripherals dai peripherals peripherals external port simd core s thermal diode fft fir iir spep bus dmd 64-bit flagx/irqx/ tmrexp wdt
rev. 0 | page 2 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 table of contents summary ............................................................... 1 revision history ...................................................... 2 general description ................................................. 3 family core architecture ........................................ 4 family peripheral architecture ................................ 7 i/o processor features ......................................... 10 system design .................................................... 11 development tools ............................................. 11 additional information ........................................ 12 related signal chains .......................................... 12 pin function descriptions ....................................... 13 specifications ........................................................ 17 operating conditions .......................................... 17 electrical characteristics ....................................... 18 absolute maximum ratings ................................... 20 esd sensitivity ................................................... 20 package information ............................................ 20 maximum power dissipation ................................. 20 timing specifications ........................................... 20 output drive currents ......................................... 54 test conditions .................................................. 54 capacitive loading .............................................. 54 thermal characteristics ........................................ 55 100-lqfp_ep lead assignment .. .............................. 57 176-lead lqfp_ep lead assignment ......................... 59 outline dimensions ................................................ 62 surface-mount design .......................................... 63 ordering guide ..................................................... 64 revision history 12/10revision 0: initial version
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 3 of 68 | december 2010 general description the adsp-2148x sharc ? processors are members of the simd sharc family of dsps th at feature analog devices super harvard architecture. the processors are source code compatible with the adsp-2 126x, adsp-2136x, adsp-2137x, adsp-2146x, and adsp-2116x ds ps, as well as with first generation adsp-2106x sharc processors in sisd (single- instruction, single-data) mode. the adsp-2148x processors are 32-bit/40-bit floating point proc essors optimized for high per- formance audio applications with large on-chip sram, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital applications interface (dai). table 1 shows performance benchmarks for the adsp-2148x processors. table 2 shows the features of the individual product offerings. table 1. processor benchmarks benchmark algorithm speed (at 400 mhz) 1024 point complex fft (radix 4, with reversal) 23 s fir filter (per tap) 1 1.25 ns iir filter (per biquad) 1 5 ns matrix multiply (pipelined) [3 3] [3 1] [4 4] [4 1] 11.25 ns 20 ns divide (y/) 7.5 ns inverse square root 11.25 ns 1 assumes two files in multichannel simd mode table 2. adsp-2148x family features feature adsp-21483 adsp-21486 adsp-21487 adsp-21488 adsp-21489 maximum instruction rate 400 mhz ram 3 mbits 5 mbits 3 mbits 5 mbits rom 4 mbits no audio decoders in rom 1 yes no pulse-width modulation 4 units (3 units on 100-lead packages) dtcp hardware accelerator contact analog devices external port interface (sdram, ami) 2 yes (16-bit) ami only yes (16-bit) serial ports 8 direct dma from sports to external port (external memory) yes fir, iir, fft accelerator yes watchdog timer yes (176-lead package only) medialb interface automotive models only idp/pdap yes uart 1 dai (sru)/dpi (sru2) yes s/pdif transceiver yes spi yes twi 1 src performance 3 C128 db thermal diode yes visa support yes package 2 176-lead lqfp epad 100-lead lqfp epad 176-lead lqfp epad 176-lead lqfp epad 100-lead lqfp epad 1 rom is factory programmed with la test multichannel audio decoding and post-process ing algorithms from dolby labs and dts. decod er/post-processor algorithm combination support varies depending upon th e chip version and the system configurations. please visit www.analog.com for compl ete information. 2 the 100-lead packages do not contain an ex ternal port. the adsp-21486 processor in the 176-lead package also does not contain a sdram controller. for more information, see 176-lead lqfp_ep lead assignment on page 59. 3 some models have C1 40 db performance. for more information, see ordering guide on page 65.
rev. 0 | page 4 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 the diagram on page 1 shows the two clock domains that make up the adsp-2148x processors. th e core clock domain contains the following features: ? two processing elements (p ex, pey), each of which com- prises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting 2x64-bit data transfers between me mory and the core at every core pro- cessor cycle ? one periodic interval timer with pinout ? on-chip sram (5 mbit) and mask-programmable rom (4 mbit) ? jtag test access port for em ulation and boundary scan. the jtag provides software debug through user break- points which allows flexible exception handling. the block diagram of the adsp-2148x on page 1 also shows the peripheral clock domain (also known as the i/o processor) which contains the following features: ?iod0 (peripheral dma) and iod1 (external port dma) buses for 32-bit data transfers ? peripheral and external port buses for core connection ? external port with an ami and sdram controller ?4 units for pwm control ? 1 memory-to-memory (mtm) unit for internal-to-internal memory transfers ? digital applications interface that includes four precision clock generators (pcg), an input data port (idp/pdap) for serial and parallel interconnects, an s/pdif receiver/transmitter, four as ynchronous sample rate con- verters, eight serial ports, and a flexible signal routing unit (dai sru). ? digital peripheral interface that includes two timers, a 2-wire interface (twi), one uart, two serial peripheral interfaces (spi), 2 precision clock generators (pcg), pulse width modulation (pwm), and a flexible signal routing unit (dpi sru2). as shown in the sharc core block diagram on page 5 , the processor uses two computational units to deliver a significant performance increase over the pr evious sharc processors on a range of dsp algorithms. with its simd computational hard- ware, the processors can perform 2.4 gflops running at 400 mhz. family core architecture the adsp-2148x is code compatible at the assembly level with the adsp-2146x, adsp-2137x, adsp-2136x, adsp-2126x, adsp-21160, and adsp-21161, an d with the first generation adsp-2106x sharc processors . the adsp-2148x shares architectural features with the adsp-2126x, adsp-2136x, adsp-2137x, adsp-2146x and adsp-2116x simd sharc processors, as shown in figure 2 and detailed in the following sections. simd computational engine the adsp-2148x contains two co mputational processing ele- ments that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and reg- ister file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. simd mode allows the processor to execute the same instruction in both processing elements, but ea ch processing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. simd mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. therefore, entering simd mode also dou- bles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transf erred with each memory or reg- ister file access. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycle and are arranged in parallel, maximizing computational throughput. single multifunction instructions execute parallel alu and multipli er operations. in simd mode, the parallel alu and multiplier operations occur in both pro- cessing elements. these comput ation units support ieee 32-bit single-precision floating-point, 40-bit extended precision float- ing-point, and 32-bit fixed-point data formats. timer the processor contains a core ti mer that can generate periodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal. data register file each processing element contains a general-purpose data regis- ter file. the register files transf er data between the computation units and the data buses, and st ore intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processors enhanced harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data registers in the register file, the dag registers, and the multiplier result register s all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 5 of 68 | december 2010 universal registers these registers can be used for general-purpose tasks. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all periph eral registers (control/status). the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm/dm data bus. these registers contain hardware to handle the data width difference. single-cycle fetch of instruction and four operands the adsp-2148x features an enha nced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data. with the its separate program and data memory buses and on- chip instruction cache, the proc essor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processor includes an on-chip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators wi th zero-overhead hardware circular buffer support the two data address generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allo w efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second- ary). the dags automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. circular buffers can start and end at any memory location. figure 2. sharc co re block diagram s s s s ss ss s s s s s ss s s ss s s ss s
rev. 0 | page 6 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the processor can conditionally execute a multiply, an add, and a subtract in both processing el ements while branching and fetch- ing up to four 32-bit values from memory, all in a single instruction. variable instruction set architecture (visa) in addition to supporting the st andard 48-bit instructions from previous sharc processors, the adsp-2148x supports new instructions of 16 and 32 bits. this feature, called variable instruction set architecture (visa), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. the program sequ encer supports fetching these 16-bit and 32-bit instructions from both internal and external sdram memory. this support is not extended to the asynchronous memory interface (ami). source modules need to be built using the visa option, in order to allow code genera- tion tools to create thes e more efficient opcodes. on-chip memory the adsp-21483 and the adsp -21488 processors contain 3 mbits of internal ram ( table 3 ) and the adsp-21486, adsp-21487, and adsp-21489 proce ssors contain 5 mbits of internal ram ( table 4 ). each memory block supports single- cycle, independent accesses by the core processor and i/o processor. the processors sram can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40- bit data), or combinations of different word sizes up to 5 mega bits. all of the memory can be accessed as 16-bit, 32-bit, 48- bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively dou- bles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. while each mem- ory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. table 3. internal memory spac e (3 mbitsadsp-21483/adsp-21488) 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 7fff block 0 rom (reserved) 0x0008 0000C0x0008 aaa9 block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 3fff block 0 sram 0x0004 9000C0x0004 cfff block 0 sram 0x0008 c000C0x0009 1554 block 0 sram 0x0009 2000C0x0009 9fff block 0 sram 0x0012 4000C0x0013 3fff reserved 0x0004 d000C0x0004 ffff reserved 0x0009 1555C0x0009 ffff reserved 0x0009 a000C0x0009 ffff reserved 0x0013 4000C0x0013 ffff block 1 rom (reserved) 0x0005 0000C0x0005 7fff block 1 rom (reserved) 0x000a 0000C0x000a aaa9 block 1 rom (reserved) 0x000a 0000C0x000a ffff block 1 rom (reserved) 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000C0x0016 3fff block 1 sram 0x0005 9000C0x0005 cfff block 1 sram 0x000a c000C0x000b 1554 block 1 sram 0x000b 2000C0x000b 9fff block 1 sram 0x0016 4000C0x0017 3fff reserved 0x0005 d000C0x0005 ffff reserved 0x000b 1555C0x000b ffff reserved 0x000b a000C0x000b ffff reserved 0x0017 4000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 1fff block 2 sram 0x000c 0000C0x000c 2aa9 block 2 sram 0x000c 0000C0x000c 3fff block 2 sram 0x0018 0000C0x0018 7fff reserved 0x0006 2000C 0x0006 ffff reserved 0x000c 2aaaC0x000d ffff reserved 0x000c 4000C0x000d ffff reserved 0x0018 8000C0x001b ffff block 3 sram 0x0007 0000C0x0007 1fff block 3 sram 0x000e 0000C0x000e 2aa9 block 3 sram 0x000e 0000C0x000e 3fff block 3 sram 0x001c 0000C0x001c 7fff reserved 0x0007 2000C0x0007 ffff reserved 0x000e 2aaaC0x000f ffff reserved 0x000e 4000C0x000f ffff reserved 0x001c 8000C0x001f ffff 1 some adsp-2147x proces sors include a customer-definable rom block. rom addres ses on these models are not reserved as shown in t his table. please contact your analog devices sales representative for additional details.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 7 of 68 | december 2010 using the dm bus and pm buses, with one bus dedicated to a memory block, assures single-c ycle execution with two data transfers. in this case, the inst ruction must be available in the cache. the memory maps in table 3 and table 4 display the internal memory address space of the processors. the 48-bit space sec- tion describes what this addr ess range looks like to an instruction that retrieves 48-bit memory. the 32-bit section describes what this address rang e looks like to an instruction that retrieves 32-bit memory. rom based security the adsp-2148x has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthorized reading from the in ternal code. when using this feature, the processor does not boot-load any external code, exe- cuting exclusively from inte rnal rom. additionally, the processor is not freely accessible via the jtag port. instead, a unique 64-bit key, which must be scanned in through the jtag or test access port will be a ssigned to each customer. the device will ignore a wrong key. emulation features are available after the correct key is scanned. on-chip memory bandwidth the internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). th e total bandwidth is realized using the dmd and pmd buses (2 64-bits, cclk speed) and the iod0/1 buses (2 32-bit, pclk speed). family peripheral architecture the adsp-2148x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3d graphics, speech recognit ion, motor control, imaging, and other applications. external memory the external port interface supports access to the external mem- ory through core and dma accesses. the external memory address space is divided into four banks. any bank can be pro- grammed as either asynchronous or synchronous memory. the external ports are comprised of the following modules. table 4. internal memory space (5 mbitsadsp-21486/ adsp-21487/adsp-21489) 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 7fff block 0 rom (reserved) 0x0008 0000C0x0008 aaa9 block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 3fff block 0 sram 0x0004 9000C0x0004 efff block 0 sram 0x0008 c000C0x0009 3fff block 0 sram 0x0009 2000C0x0009 dfff block 0 sram 0x0012 4000C0x0013 bfff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 ffff reserved 0x0009 e000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 1 rom (reserved) 0x0005 0000C0x0005 7fff block 1 rom (reserved) 0x000a 0000C0x000a aaa9 block 1 rom (reserved) 0x000a 0000C0x000a ffff block 1 rom (reserved) 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000C0x0016 3fff block 1 sram 0x0005 9000C0x0005 efff block 1 sram 0x000a c000C0x000b 3fff block 1 sram 0x000b 2000C0x000b dfff block 1 sram 0x0016 4000C0x0017 bfff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b ffff reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 3fff block 2 sram 0x000c 0000C0x000c 5554 block 2 sram 0x000c 0000C0x000c 7fff block 2 sram 0x0018 0000C0x0018 ffff reserved 0x0006 4000C 0x0006 ffff reserved 0x000c 5555C0x000d ffff reserved 0x000c 8000C0x000d ffff reserved 0x0019 0000C0x001b ffff block 3 sram 0x0007 0000C0x0007 3fff block 3 sram 0x000e 0000C0x000e 5554 block 3 sram 0x000e 0000C0x000e 7fff block 3 sram 0x001c 0000C0x001c ffff reserved 0x0007 4000C0x0007 ffff reserved 0x000e 5555C0x0000f ffff reserved 0x000e 8000C0x000f ffff reserved 0x001d 0000C0x001f ffff 1 some adsp-2148x processors incl ude a customer-definable rom block and are not rese rved as shown on this table. please contact y our analog devices sales representative for additional details.
rev. 0 | page 8 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 ? an asynchronous memory in terface which communicates with sram, flash, and other devices that meet the stan- dard asynchronous sram access protocol. the ami supports 6m words of external memory in bank 0 and 8m words of external memory in bank 1, bank 2, and bank 3. ? a sdram controller that supports a glueless interface with any of the standard sdra ms. the sdc supports 62m words of external memory in bank 0, and 64m words of external memory in bank 1, bank 2, and bank 3. note: this feature is not available on the adsp-21486 product. ? arbitration logic to coordinate core and dma transfers between internal and external memory over the external port. non-sdram external memory address space is shown in table 5 . external port the external port provides a hi gh performance, glueless inter- face to a wide variety of industry-standard memory devices. the external port, available on the 176-lead lqfp, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. the first is an sdram controller fo r connection of industry-stan- dard synchronous dram devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to co exist, supporting any desired com- bination of synchronous and asynchronous device types. asynchronous memory controller the asynchronous memory contro ller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing paramete rs, enabling connection to a wide variety of memory devices including sram, flash, and eprom, as well as i/o devices that interface with standard memory control lines. bank 0 occupies a 6m word window and banks 1, 2, and 3 occupy a 8m word window in th e processors address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. sdram controller the sdram controller provides an interface of up to four sepa- rate banks of industry-standard sdram devices at speeds up to f sdclk . fully compliant with the sdram standard, each bank has its own memory select line (ms0 Cms3 ), and can be configured to contain between 4m bytes and 256m bytes of memory. sdram external memory ad dress space is shown in table 6 . note: this feature is not available on the adsp-21486 model. a set of programmable timing parameters is available to config- ure the sdram banks to support slower memory devices. note that 32-bit wide devices are not supported on the sdram and ami interfaces. the sdram controller address, data, clock, and control pins can drive loads up to distributed 30 pf. for larger memory sys- tems, the sdram controller external buffer timing should be selected and external buffering sh ould be provided so that the load on the sdram controller pins does not exceed 30 pf. note that the external memory bank addresses shown are for normal-word (32-bit) accesses. if 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. simd access to external memory the sdram controller on the pr ocessor supports simd access on the 64-bit epd (external port data bus) which allows to access the complementary register s on the pey unit in the nor- mal word space (nw). this impr oves performance since there is no need to explicitly load the complimentary registers as in sisd mode. visa and isa access to external memory the sdram controller on the adsp-2148x processors sup- ports visa code operation which reduces the memory load since the visa instructions are compressed. moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. code execution from the tra- ditional isa operation is also supported. note that code execution is only supported from bank 0 regardless of visa/isa. table 7 shows the address ranges for instruction fetch in each mode. table 5. external memory for non-sdram addresses bank size in words address range bank 0 6m 0x0020 0000C0x007f ffff bank 1 8m 0x0400 0000C0x047f ffff bank 2 8m 0x0800 0000C0x087f ffff bank 3 8m 0x0c00 0000C0x0c7f ffff table 6. external memory for sdram addresses bank size in words address range bank 0 62m 0x0020 0000C0x03ff ffff bank 1 64m 0x0400 0000C0x07ff ffff bank 2 64m 0x0800 0000C0x0bff ffff bank 3 64m 0x0c00 0000C0x0fff ffff table 7. external bank 0 instruction fetch access type size in words address range isa (nw) 4m 0x0020 0000C0x005f ffff visa (sw) 10m 0x0060 0000C0x00ff ffff
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 9 of 68 | december 2010 pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programmed to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs generating 16 pwm outputs in total. each pwm group pro- duces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single-update mode or double-update mode. in single-update mode the duty cycle values are programmable only once per pwm period. this results in pw m patterns that are symmetri- cal about the midpoint of the pwm period. in double-update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic distortion in three-phase pwm inverters. pwm signals can be ma pped to the external port address lines or to the dpi pins. medialb the automotive models of the adsp-2148x pr ocessors have an mlb interface which allows the processor to function as a media local bus device. it includes support for both 3-pin as well as 5-pin media local bus protocol s. it supports speeds up to 1024 fs (49.25 mbits/sec, fs = 48. 1 khz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. for a list of automotive products, see automotive products on page 64 . digital applications interface (dai) the digital applications interface (dai) allows the connection of various peripherals to any of the dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru). the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. the dai also includes eight serial ports, four precision clock generators (pcg), a s/pdif transceiver, four asrcs, and an input data port (idp). the idp provides an additional input path to the sharc core, configur able as either eight channels of serial data, or a single 20-bi t wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independent from th e processors serial ports. serial ports (sports) the adsp-2148x features eight sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports can support up to 16 transmit or 16 receive dma channels of audio data when all eight sports are enabled, or four full duplex tdm stream s of 128 channels per frame. serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provid e tdm support. one sport pro- vides two transmit signals whil e the other sport provides the two receive signals. the fram e sync and clock are shared. serial ports operate in five modes: ? standard serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode s/pdif-compatible digital audio receiver/transmitter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/transmitter can be formatted as left-justified, i 2 s or right-justified with word widths of 16, 18, 20, or 24 bits. the serial data, clock, and fram e sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources, such as the sports, external pins, or the precision clock generators (pcgs), and are controlled by the sru control registers. asynchronous sample rate converter (src) the asynchronous sample rate converter contains four src blocks and is the same core as that used in the ad1896 192 khz stereo asynchronous sample rate converter and provides up to 128 db snr. the src block is used to perform synchronous or asynchronous sample rate conver sion across independent stereo channels, without using internal processor resources. the four src blocks can also be config ured to operate together to convert multichannel audio data without phase mismatches. finally, the src can be used to clean up audio data from jittery clock sources such as the s/pdif receiver. input data port the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided
rev. 0 | page 10 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 into two 32-bit words. the serial protocol is designed to receive audio channels in i 2 s, left-justified sample pair, or right-justified mode. the idp also provides a parallel data acquisition port (pdap), which can be used for receivin g parallel data. the pdap port has a clock input and a hold input. the data for the pdap can be received from dai pins or fr om the external port pins. the pdap supports a maximum of 20-bit data and four different packing modes to recei ve the incoming data. precision clock generators the precision clock generators (pcg) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. the units, a b, c, and d, are identical in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. the outputs of pcg a and b ca n be routed through the dai pins and the outputs of pcg c and d can be driven on to the dai as well as the dpi pins. digital peripheral interface (dpi) the adsp-2148x sharc processors have a digita l peripheral interface that provid es connections to two serial peripheral interface ports (spi), one universal asynchronous receiver- transmitter (uart), 12 flags, a 2-wire interface (twi), three pwm modules (pwm3C1), and tw o general-purpose timers. serial peripheral (compatible) interface (spi) the spi is an industry-stand ard synchronous serial link, enabling the spi-compatible po rt to communicate with other spi compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchro- nous serial interface, supporting both master and slave modes. the spi port can operate in a multimaster environment by interfacing with up to four othe r spi-compatible devices, either acting as a master or slave de vice. the spi-compatible periph- eral implementation also featur es programmable baud rate and clock phase and polarities. the spi-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. uart port the processors provide a full-duplex universal asynchronous receiver/transmitter (uart) port , which is fully compatible with pc-standard uarts. the ua rt port provides a simpli- fied uart interface to other pe ripherals or ho sts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. the uart also has mult iprocessor communication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through the rs-485 data interface standard. the uart port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o)the pr ocessor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. timers the adsp-2148x has a total of th ree timers: a core timer that can generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be independently set to operat e in one of three modes: ?pulse waveform generation mode ?pulse width co unt/capture mode ? external event watchdog mode the core timer can be configured to use flag3 as a timer expired signal, and the general-pu rpose timers have one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables the general- purpose timer. 2-wire interface port (twi) the twi is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? 7-bit addressing ? simultaneous master and slave operation on multiple device systems with support for multi master data arbitration ? digital filtering and timed event processing ? 100 kbps and 400 kbps data rates ? low interrupt rate i/o processor features the i/o processors provide up to 65 channels of dma, as well as an extensive set of peripherals. dma controller the processors on-chip dma cont roller allows data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the adsp-2148xs internal memory and its serial ports, the spi-compatible (serial periph eral interface) ports, the idp (input data port), the pdap, or the uart. the dma channel summary is shown in table 8 .
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 11 of 68 | december 2010 programs can be downloaded to the adsp-2148x using dma transfers. other dma features include interrupt generation upon completion of dma transfers and dma chaining for automatic linked dma transfers. delay line dma the processor provides delay li ne dma functionality. this allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. scatter/gather dma the processor provides scatter/ga ther dma functionality. this allows processor dma reads/writes to/from non contiguous memory blocks. fft accelerator the fft accelerator implements a radix-2 complex/real input, complex output fft with no core intervention. the fft accel- erator runs at the peripheral clock frequency. fir accelerator the fir (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four mac units. a controller manages the accelerator. the fir accelerator runs at the peripheral clock frequency. iir accelerator the iir (infinite impulse response) accelerator consists of a 1440 word coefficient memory fo r storage of biquad coeffi- cients, a data memory for storin g the intermediate data, and one mac unit. a controller manages th e accelerator. the iir accel- erator runs at the peripheral clock frequency. watchdog timer the watchdog timer is used to su pervise the stability of the sys- tem software. when used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires. an expiring timer then indicates that system software mi ght be out of control. the 32-bit watchdog timer that can be used to implement a soft- ware watchdog function. a software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset, if the timer expires before being reloaded by software. soft ware initializes the count value of the timer, and then enables the timer. the watchdog timer resets both the core and the internal peripherals. note that this feature is available on the 176-lead package only. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the adsp-2148x boots at system power-up from an 8-bit eprom via the external port, an spi master, or an spi slave. booting is determined by the boot con- figuration (boot_cfg2C0) pins in table 9 for the 176-lead package and table 10 for the 100-lead package. the running reset feature allows a user to perform a reset of the processor core and peripherals, but without resetting the pll and sdram controller, or performing a boot. the functionality of the resetout /runrstin pin has now been extended to also act as the inpu t for initiating a running reset. for more information, see the adsp-214xx sharc processor hardware reference . power supplies the processors have separate power supply connections for the internal (v dd_int ) and external (v dd_ext ) power supplies. the internal supply must meet the v dd_int specifications. the external supply must meet the v dd_ext specification. all exter- nal supply pins must be connec ted to the same power supply. to reduce noise coupling, the pc b should use a parallel pair of power and ground planes for v dd_int and gnd. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access port of the adsp-2148x pro- cessors to monitor and control the target board processor table 8. dma channels peripheral dma channels sports 16 idp/pdap 8 spi 2 uart 2 external port 2 accelerators 2 memory-to-memory 2 mlb 1 1 automotive models only. 31 table 9. boot mode selection, 176-lead package boot_cfg2C0 booting mode 000 spi slave boot 001 spi master boot 010 ami user boot (for 8-bit flash boot) 011 no boot (processor executes from internal rom after reset) 1xx reserved table 10. boot mode selection, 100-lead package boot_cfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 reserved 11 no boot (processor executes from internal rom after reset)
rev. 0 | page 12 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 during emulation. analog devices dsp tools product line of jtag emulators provides emulat ion at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks. the processors jtag interface ensures that the emulator will not affect targ et system load ing or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the adsp-2148x processors are su pported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++ ? development environment. the sa me emulator hardware that supports other sharc processors also fully emulates the adsp-2148x processors. ez-kit lite evaluation board for evaluation of the processors, use the ez-kit lite ? board from analog devices. the boar d comes with on-chip emulation capabilities and is eq uipped to enable so ftware development. multiple daughter cards are available. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in- circuit emulation is assured by the use of the processors jtag interfacethe emulator does not af fect target system loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping applic ations with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board alon g with an evaluation suite of the visualdsp++ ? development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot co de, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high speed, non- intrusive emulation. additional information this data sheet provides a general overview of the adsp-2148x architecture and functionality. for detailed information on the adsp-2148x family core architecture and instruction set, refer to the sharc processor programming reference . related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the circuits from the lab tm site ( www.analog.com/circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 13 of 68 | december 2010 pin function descriptions table 11. pin descriptions name type state during/ after reset description addr 23C0 i/o/t (ipu) high-z/ driven low (boot) external address. the processor outputs addresses for external memory and periph- erals on these pins. the addr pins can be multiplexed to support the external memory interface address, and flags15C 8 (i/o) and pwm (o). after reset, all addr pins are in external memory interface mode and flag(0 C3) pins are in flags mode (default). when configured in the idp_pdap_ctl register, idp channel 0 scans the addr 23C4 pins for parallel input data. data 15C0 i/o/t (ipu) high-z external data. the data pins can be multiplexed to support the external memory interface data (i/o), and flags 7C0 (i/o). ami_ack i (ipu) memory acknowledge. external devices can deassert ami_ack (low) to add wait states to an external memory access. ami_ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. ms 0C1 o/t (ipu) high-z memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory. the ms 1-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 1-0 lines are inactive; they are active however when a condi- tional memory access instruction is executed, whether or not the condition is true. the ms1 pin can be used in eport/flash boot mode. for more information, see the adsp-214xx sharc processor hardware reference . ami_rd o/t (ipu) high-z ami port read enable. ami_rd is asserted whenever the processor reads a word from external memory. ami_wr o/t (ipu) high-z ami port write enable. ami_wr is asserted when the processor writes a word to external memory. flag0/irq0 i/o (ipu) flag[0] input flag0/interrupt request0. flag1/irq1 i/o (ipu) flag[1] input flag1/interrupt request1. flag2/irq2 /ms2 i/o (ipu) flag[2] input flag2/interrupt request2/memory select2. flag3/tmrexp/ms3 i/o (ipu) flag[3] input flag3/timer expired/memory select3. the following symbols appear in the type column of table 11 : a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k. in this table, all pins are lvttl compliant with the exception of the thermal diode pins.
rev. 0 | page 14 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 sdras o/t (ipu) high-z/ driven high sdram row address strobe. connect to sdrams ras pin. in conjunction with other sdram command pins, defines the opera tion for the sdram to perform. sdcas o/t (ipu) high-z/ driven high sdram column address select. connect to sdrams cas pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdwe o/t (ipu) high-z/ driven high sdram write enable. connect to sdrams we or w buffer pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdcke o/t (ipu) high-z/ driven high sdram clock enable. connect to sdrams cke pin. enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sda10 o/t (ipu) high-z/ driven high sdram a10 pin. enables applications to refresh an sdram in parallel with non-sdram accesses. this pin replaces the dsps addr10 pin only during sdram accesses. sddqm o/t (ipu) high-z/ driven high dqm data mask. sdram input mask signal for write accesses and output mask signal for read accesses. input data is masked when dqm is sampled high during a write cycle. the sdram output buffers are placed in a high-z state when dqm is sampled high during a read cycle. sddqm is driven high from reset de-assertion until sdram initial- ization completes. afterwards it is driven low irrespective of whether any sdram accesses occur or not. sdclk o/t (ipd) high-z/ driving sdram clock output. clock driver for this pin differs from all other clock drivers. see figure 41 on page 54 . dai _p 20C1 i/o/t (ipu) high-z digital applications interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audio- centric peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dai sru may be routed to any of these pins. dpi _p 14C1 i/o/t (ipu) high-z digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configu- ration registers of these peripherals then de termines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. wdt_clkin i watchdog timer clock input. this pin should be pulled low when not used. wdt_clko o watchdog resonator pad output. wdtrsto o (ipu) watchdog timer reset out. thd_p i thermal diode anode. when not used, this pin can be left floating. thd_m o thermal diode cathode. when not used, this pin can be left floating. table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11 : a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k. in this table, all pins are lvttl compliant with the exception of the thermal diode pins.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 15 of 68 | december 2010 mlbclk 1 i media local bus clock. this clock is generated by the mlb controller that is synchro- nized to the most network and provides the timing for the entire mlb interface at 49.152 mhz at fs=48 khz. when the mlb co ntroller is not used, this pin should be grounded. mlbdat 1 i/o/t in 3 pin mode. i in 5 pin mode. high-z media local bus data. the mlbdat line is driven by the transmitting mlb device and is received by all other mlb devices incl uding the mlb controller. the mlbdat line carries the actual data. in 5-pin mlb mode, this pin is an input only. when the mlb controller is not used, this pin should be grounded. mlbsig 1 i/o/t in 3 pin mode. i in 5 pin mode high-z media local bus signal. this is a multiplexed signal which carries the channel/address generated by the mlb controller, as well as the command and rxstatus bytes from mlb devices. in 5-pin mode, this pin is input only. when the mlb controller is not used, this pin should be grounded. mlbdo 1 o/t high-z media local bus data output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output data pin in 5-pin mode. when the mlb controller is not used, this pin should be connected to ground. mlbso 1 o/t high-z media local bus signal output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output signal pin in 5-pin mode. when the mlb controller is not used, this pin should be connected to ground. tdi i (ipu) test data input (jtag). provides serial data for the boundary scan logic. tdo o/t high-z test data output (jtag). serial scan output of the boundary scan path. tms i (ipu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the device. trst i (ipu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. emu o/t (ipu) high-z emulation status. must be connected to the adsp-2148x analog devices dsp tools product line of jtag emulators target board connector only. table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11 : a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k. in this table, all pins are lvttl compliant with the exception of the thermal diode pins.
rev. 0 | page 16 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 clk_cfg 1C0 i core to clkin ratio control. these pins set the start up clock frequency. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any t ime after the core comes out of reset. the allowed values are: 00 = 8:1 01 = 32:1 10 = 16:1 11 = reserved clkin i local clock in. used in conjunction with xtal. clkin is the clock input. it configures the processors to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processors to use the external clock source such as an external clock oscillator. clkin may not be halted, ch anged, or operated below the specified frequency. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. reset i processor reset. resets the processor to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. resetout / runrstin i/o (ipu) reset out/running reset in. the default setting on this pin is reset out. this pin also has a second function as runrstin which is enabled by setting bit 0 of the runrstctl register. for more information, see the adsp-214xx sharc processo r hardware reference . boot_cfg 2C0 i boot configuration select. these pins select the boot mode for the processor (see table 9 ). the boot_cfg pins must be valid before reset (hardware and software) is asserted. 1 the mlb pins are only availabl e on the automotive models. table 12. pin list, power and ground name type description v dd_int p internal power supply v dd_ext p i/o power supply gnd 1 g ground v dd_thd p thermal diode power supply . when not used, this pin can be left floating. 1 the exposed pad is required to be electric ally and thermally connected to gnd. implement this by soldering the exposed pad to a gnd pcb land that is the same size as the exposed pad. the gnd pcb land should be robustly connected to the gnd plane in the pcb for best electrical and thermal performance. no se parate gnd pins are provided in the package. table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11 : a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be pr ogrammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k. in this table, all pins are lvttl compliant with the exception of the thermal diode pins.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 17 of 68 | december 2010 specifications operating conditions 300 mhz 350 mhz 400 mhz unit parameter 1 1 specifications subject to change without notice. description min nom max min nom max min nom max v dd_int internal (core) supply voltage 1.05 1.1 1.15 1.05 1.1 1.15 1.05 1.1 1.15 v v dd_ext external (i/o) supply voltage 3.13 3.47 3.13 3.47 3.13 3.47 v v dd_thd thermal diode supply voltage 3.13 3.47 3.13 3.47 3.13 3.47 v v ih 2 2 applies to input and bidirecti onal pins: addr23C0, data15C0, flag3C0, dai_ px, dpi_px, boot_cfgx, clk_cfgx, runrstin , reset , tck, tms, tdi, trst , ami_ack, mlbclk, mlbdat, mlbsig. high level input voltage @ v dd_ext = max 2.0 3.6 2.0 3.6 2.0 3.6 v v il 4 low level input voltage @ v dd_ext = min C0.3 0.8 C0.3 0.8 C0.3 0.8 v v ih_clkin 3 3 applies to input pins clkin, wdt_clkin. high level input voltage @ v dd_ext = max 2.2 v dd_ext 2.2 v dd_ext 2.2 v dd_ext v v il_clkin low level input voltage @ v dd_ext = min C0.3 +0.8 C0.3 +0.8 C0.3 +0.8 v t j junction temperature 100-lead lqfp_ep @ t ambient 0c to +70c 0 110 0 110 0 110 c t j junction temperature 100-lead lqfp_ep @ t ambient C40c to +85c C40 125 C40 125 C40 125 c t j junction temperature 176-lead lqfp_ep @ t ambient 0c to +70c 0 110 0 110 0 110 c t j junction temperature 176-lead lqfp_ep @ t ambient C40c to +85c C40 125 C40 125 C40 125 c
rev. 0 | page 18 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 electrical characteristics 300 mhz 350 mhz 400 mhz parameter 1 description test conditions min max min max min max unit v oh 2 high level output voltage @ v dd_ext = min, i oh = C1.0 ma 3 2.4 2.4 2.4 v v ol 2 low level output voltage @ v dd_ext = min, i ol = 1.0 ma 3 0.4 0.4 0.4 v i ih 4, 5 high level input current @ v dd_ext = max, v in = v dd_ext max 10 10 10 a i il 4 low level input current @ v dd_ext = max, v in = 0 v 10 10 10 a i ilpu 5 low level input current pull-up @ v dd_ext = max, v in = 0 v 200 200 200 a i ozh 6, 7 three-state leakage current @ v dd_ext = max, v in = v dd_ext max 10 10 10 a i ozl 6 three-state leakage current @ v dd_ext = max, v in = 0 v 10 10 10 a i ozlpu 7 three-state leakage current pull-up @ v dd_ext = max, v in = 0 v 200 200 200 a i ozhpd 8 three-state leakage current pull- down @ v dd_ext = max, v in = v dd_ext max 200 200 200 a i dd-intyp 9, 10 supply current (internal) v ddint =1.1 v, asf = 1, t j = 25c 410 450 500 ma c in 11, 12 input capacitance t case = 25c 5 5 5 pf 1 specifications subject to change without notice. 2 applies to output and bidirectional pins: addr23C0, data15C0, ami_rd , ami_wr , flag3C0, dai_px, dpi_px, emu , tdo, resetout mlbsig, mlbdat, mlbdo, mlbso, sdras , sdcas , sdwe , sdcke, sda10, sddqm, ms0-1 . 3 see output drive currents on page 54 for typical drive current capabilities. 4 applies to input pins: boot_cfgx, clk_cfgx, tck, reset , clkin. 5 applies to input pins with internal pull-ups: trst , tms, tdi. 6 applies to three-statable pin: tdo. 7 applies to three-statable pins with pull-ups: dai_px, dpi_px, emu . 8 applies to three-statable pin with pull-down: sdclk. 9 typical internal current data reflects nominal operating conditions. 10 see engineer-to-engineer note estimating power dissipation for adsp-2 14xx sharc processors (ee-348) for further information. 11 applies to all signal pins. 12 guaranteed, but not tested.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 19 of 68 | december 2010 total power dissipation total power dissipation has two components: 1. internal power consumption 2. external power consumption internal power consumption al so comprises two components: 1. static, due to leakage current. table 13 shows the static cur- rent consumption (i dd-static ) as a function of junction temperature (t j ) and core voltage (v dd_int ). 2. dynamic (i dd-dynamc ), due to transistor switching char- acteristics and activity level of the processor. the activity level is reflected by the activity scaling factor (asf), which represents application code ru nning on the processor core and having various levels of peripheral and external port activity ( table 13 ). dynamic current consumption is calcu- lated by scaling the specific application by the asf and using baseline dynamic current consumption as a reference. external power consumption is due to the switching activity of the external pins. the asf is combined with the cclk frequency and v dd_int dependent data in table 14 to calculate this part. the second part is due to transistor swit ching in the peripheral clock (pclk) domain, which is included in the i dd_int specification equation. table 13. activity scaling factors (asf) 1 1 see estimating power for adsp-214 xx sharc processors (ee-348) for more information on the explanation of the po wer vectors specific to the asf table. activity scaling factor (asf) idle 0.29 low 0.53 medium low 0.61 medium high 0.77 peak typical (50:50) 2 2 ratio of continuous instruction loop (c ore) to sdram control code reads and writes. 0.85 peak typical (60:40) 2 0.93 peak typical (70:30) 2 1.00 high typical 1.16 high 1.25 peak 1.31 table 14. static currenti dd-static (ma) 1 t j (c) v dd_int (v) 1.05 v 1.10 v 1.15 v C45 96 118 144 C35 103 126 154 C25 113 138 168 C15 127 155 187 C5 147 177 212 +5 171 206 245 +15 201 240 285 +25 237 280 331 +35 279 329 388 +45 331 389 455 +55 391 458 533 +65 464 539 626 +75 547 633 731 +85 645 746 860 +95 761 877 1007 +105 897 1026 1179 +115 1047 1198 1372 +125 1219 1397 1601 1 valid temperature and voltage ranges are model-specific. see operating condi- tions on page 17 . table 15. baseline dynamic current in cclk domain (ma, with asf = 1.0) 1, 2 f cclk (mhz) voltage (v dd_int ) 1.05 v 1.10 v 1.15 v 100 84 88 92 150 126 133 139 200 165 174 183 250 207 217 229 300 246 260 273 350 286 302 318 400 326 344 361 1 the values are not guaranteed as standalo ne maximum specifications. they must be combined with static c urrent per the equations of electrical characteristics on page 18 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions on page 17 .
rev. 0 | page 20 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 absolute maximum ratings stresses greater than those listed in table 16 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package information the information presented in figure 3 provides details about the package branding for the adsp-2148x processors. for a complete listing of pr oduct availability, see ordering guide on page 65 . esd sensitivity maximum power dissipation see engineer-to-engineer note estimating power dissipation for adsp-214xx sharc processo rs (ee-348) for detailed thermal and power information regarding maximum power dis- sipation. for information on pack age thermal specifications, see thermal characteristics on page 55 . timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 43 on page 54 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to en sure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing internal memory, the processor core, and the serial ports. during reset, program the ratio between the processors internal clock frequency and external (clkin) clock frequency with the clk_cfg1C0 pins. the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an in ternal phase-locked loop (pll, see figure 4 ). this pll-based clocki ng minimizes the skew between the system clock (clkin ) signal and the processors internal clock. table 16. absolute maximum ratings parameter rating internal (core) supply voltage (v dd_int ) C0.3 v to +1.32 v external (i/o) supply voltage (v dd_ext )C0.3 v to +3.6 v thermal diode supply voltage (v dd_thd ) C0.3 v to +3.6 v input voltage C0.5 v to +3.6 v output voltage swing C0.5 v to v dd_ext +0.5 v storage temperature range C65c to +150c junction temperature while biased 125c figure 3. typical package brand table 17. package br and information brand key field description t temperature range pp package type z rohs compliant option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppz-cc s s a esd (electrostatic discharge) sensitive device. charged devic es and c irc uit boards c an disc harge without detection. although this product features patented or proprietary protec tion c irc uitry, damage may o ccur on devic es subjec ted to high energy esd. t herefore, proper esd prec autions shoul d be taken to avoid performanc e degradation or loss of functionality.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 21 of 68 | december 2010 voltage controlled oscillator (vco) in application designs, the p ll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 20 . ? the product of clkin and pllm must never exceed 1/2 of f vco (max) in table 20 if the input divider is not enabled (indiv = 0). ? the product of clkin and pllm must never exceed f vco (max) in table 20 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) plld where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plld = 2, 4, 8, or 16 based on the divider value programmed on the pmctl register. during reset this value is 2. f input = is the input frequency to the pll. f input = clkin when the input divider is disabled or f input = clkin 2 when the input divider is enabled note the definitions of the clock periods that are a function of clkin and the appropriate ratio control shown in table 18 . all of the timing specifications fo r the adsp-2148x peripherals are defined in relation to t pclk . see the peripheral specific section for each peripherals timing information. figure 4 shows core to clkin relati onships with external oscil- lator or crystal. the shaded di vider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (pmctl). for more information, see the adsp-214xx sharc processor hard- ware reference. table 18. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk t sdclk sdram clock period = (t cclk ) sdckr figure 4. core clock and system clock relationship to clkin loop filter clkin pclk sdram divider bpass mux pmctl (sdckr) cclk pll xtal clkin divider reset co m u co u mct idi diider resetout couttesto deao ci cces c mct mct d co cc iut couttestoreuecistesameas iut tissiaisotseciiedorsuortedoradesi c_cx mctm diide i mu mct cc resetout coresrst sdc ass mu
rev. 0 | page 22 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 power-up sequencing the timing requirements for pr ocessor startup are given in table 19 . while no specific power-up sequencing is required between v dd_ext and v dd_int , there are some considerations that system designs should take into account. ? no power supply should be powered up for an extended period of time (> 200 ms) befo re another supply starts to ramp up. ?if the v dd_int power supply comes up after v dd_ext , any pin, such as resetout and reset , may actually drive momentarily until the v dd_int rail has powered up. systems sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior. note that during power-up, when the v dd_int power supply comes up after v dd_ext , a leakage current of the order of three- state leakage current pull-up, pull-down may be observed on any pin, even if that is an in put only (for example the reset pin) until the v dd_int rail has powered up. table 19. power up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v dd_ext or v dd_int on 0 ms t ivddevdd v dd_int on before v dd_ext C200 +200 ms t clkvdd 1 clkin valid after v dd_int and v dd_ext valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 ms t pllrst pll control setup before reset deasserted 20 3 ms switching characteristic t corerst 4, 5 core reset deasserted after reset deasserted 4096 t ck + 2 t cclk ms 1 valid v dd_int and v dd_ext assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). voltage r amp rates can vary from microseconds to hundreds of milliseconds depending on the des ign of the power supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturer's data sheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin an d internal oscillator circuit in conjunction with an external c rystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subsequent resets require a minimum of four clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 21 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 5. power-up sequencing t rstvdd t clkvdd t clkrst t corerst t pllrst v ddext v ddint clkin clk_cfg1C0 reset resetout t ivddevdd
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 23 of 68 | december 2010 clock input clock signals the adsp-2148x can use an external clock or a crystal. see the clkin pin description in table 11 on page 13 . programs can configure the processor to use its internal clock generator by connecting the necessary comp onents to clkin and xtal. figure 7 shows the component connec tions used for a crystal operating in fundamental mode. note that the clock rate is achieved using a 25 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 400 mhz). to achieve the full core clock rate, programs need to configure the multi- plier bits in the pmctl register. table 20. clock input parameter 300 mhz 350 mhz 400 mhz unit min max min max min max timing requirements t ck clkin period 26.66 1 1 applies only for clk_cfg1C0 = 00 and defa ult values for pll control bits in pmctl. 100 2 2 applies only for clk_cfg1C0 = 01 and defa ult values for pll control bits in pmctl. 22.8 1 100 2 20 1 100 2 ns t ckl clkin width low 134511451045ns t ckh clkin width high 13 45 11 45 10 45 ns t ckrf 3 3 guaranteed by simulation but not tested on silicon. clkin rise/fall (0.4 v to 2.0 v) 3 3 3 ns t cclk 4 4 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 3.33 10 2.85 10 2.5 10 ns f vco 5 5 see figure 4 on page 21 for vco diagram. vco frequency 200 600 200 700 200 800 mhz t ckj 6, 7 6 actual input jitter should be combined with ac specifications for acc urate timing analysis. 7 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 C250 +250 C250 +250 ps figure 6. clock input clkin t ck t ckl t ckh t ckj figure 7. recommended circuit for fundamental mode crystal operation c1 22pf y1 r1 1m * xtal clkin c2 22pf 25 mhz r2 47 * *typical values adsp-2148x r2 should be chosen to limit crystal drive power. refer to crystal manufacturers specifications
rev. 0 | page 24 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 reset running reset the following timing specification applies to resetout/runrstin pin when it is configured as runrstin . table 21. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4 t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the proces sors internal phase-locked l oop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 8. reset clkin reset t srst t wrst table 22. running reset parameter min max unit timing requirements t wrunrst running reset pulse width low 4 t ck ns t srunrst running reset setup before clkin high 8 ns figure 9. running reset clkin runrstin t wrunrst t srunrst
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 25 of 68 | december 2010 interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts, as well as the dai_p20C1 and dpi_p14C1 pins when they ar e configured as interrupts. core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp). table 23. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 10. interrupts interrupt inputs t ipw table 24. core timer parameter min max unit switching characteristic t wctim tmrexp pulse width 4 t pclk C 1 ns figure 11. core timer flag3 (tmrexp) t wctim
rev. 0 | page 26 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 timer pwm_out cycle timing the following timing specification applies to timer0 and timer1 in pwm_out (pulse-width modu lation) mode. timer signals are routed to the dpi_p14C1 pi ns through the dpi sru. there- fore, the timing specifications provided below are valid at the dpi_p14C1 pins. timer wdth_cap timing the following timing specification applies to timer0 and timer1, and in wdth_cap (pulse-width count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specification provided below is valid at the dpi_p14C1 pins. table 25. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1.2 2 (2 31 C 1) t pclk ns figure 12. timer pwm_out timing pwm outputs t pwmo table 26. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 13. timer width capture timing timer capture inputs t pwi
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 27 of 68 | december 2010 watchdog timer timing pin to pin direct routing (dai and dpi) for direct pin connections only (for example dai_pb01_i to dai_pb02_o). table 27. watchdog timer timing parameter min max unit timing requirement t wdtclkper 100 1000 ns switching characteristics t rst wdt clock rising edge to watchdog timer reset falling edge 36.4 ns t rstpw reset pulse width 64 t wdtclkper ns figure 14. watchdog timer timing wdt_clkin wdtrsto t wdtclkper t rst t rstpw table 28. dai/dpi pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai/dpi output valid 1.5 12 ns figure 15. dai pin to pin direct routing dai_pn dpi_pn dai_pm dpi_pm t dpio
rev. 0 | page 28 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers), there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 29. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgiw input clock period t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip ) 10 + (2.5 t pcgip )n s t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-214xx sharc processor hardware reference , precision clock generators chapter. 1 normal mode of operation. figure 16. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pck_clkx_o dai_pz dpi_pz pcg_fsx_o t dtrigfs t dtrigclk t dpcgio t strig t htrig t pcgow t dpcgio t pcgiw
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 29 of 68 | december 2010 flags the timing specifications provided below apply to addr7C0 and data7C0 when config ured as flags. see table 11 on page 13 for more information on flag use. table 30. flags parameter min max unit timing requirement t fipw 1 flags in pulse width 2 t pclk + 3 ns switching characteristic t fopw 1 flags out pulse width 2 t pclk C 3 ns 1 this is applicable when the flags are connected to dpi_p14C1, addr7C0, data7C0 and flag3C0 pins. figure 17. flags flag inputs flag outputs t fopw t fipw
rev. 0 | page 30 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 sdram interface timing (166 mhz sdclk) table 31. sdram interface timing parameter min max unit timing requirement s t ssdat data setup before sdclk 0.7 ns t hsdat data hold after sdclk 1.23 ns switching characteristic s t sdclk 1 1 systems should use the sdram model with a speed grade higher than the desired sdram controller speed. for example, to run the s dram controller at 166 mhz the sdram model with a speed grade of 183 mhz or above should be used. see engineer-t o-engineer note interfacing sdram memory to s harc processors (ee-286) for more information on hardware design guidelines for the sdram interface. sdclk period 6 ns t sdclkh sdclk width high 2.2 ns t sdclkl sdclk width low 2.2 ns t dcad 2 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdcke. command, addr, data delay after sdclk 4 ns t hcad 2 command, addr, data hold after sdclk 1 ns t dsdat data disable after sdclk 5.3 ns t ensdat data enable after sdclk 0.3 ns figure 18. sdram interface timing sdclk data (in) data (out) command/addr (out) t sdclkh t sdclkl t hsdat t ssdat t hcad t dcad t ensdat t dcad t dsdat t hcad t sdclk
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 31 of 68 | december 2010 ami read use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 32. ami read parameter min max unit timing requirements t dad 1, 2 address selects delay to data valid w + t sdclk C5.4 ns t drld 1 ami_rd low to data valid w C 3.2 ns t sds data setup to ami_rd high 2.5 ns t hdrh 3, 4 data hold from ami_rd high 0 ns t daak 2, 5 ami_ack delay from address, selects t sdclk C9.5 + w ns t dsak 4 ami_ack delay from ami_rd low w C 7 ns switching characteristics t drha address selects hold after ami_rd high rhc + 0.20 ns t darl 2 address selects to ami_rd low t sdclk C 3.8 ns t rw ami_rd pulse width w C 1.4 ns t rwr ami_rd high to ami_rd low hi + t sdclk C 1 ns w = (number of wait states specified in amictlx register) t sdclk . rhc = (number of read hold cycles specified in amictlx register) t sdclk where predis = 0 hi = rhc: read to read from same bank hi = rhc + ic: read to read from different bank hi = rhc + max (ic, (4 t sdclk )) : read to write from same or different bank where predis = 1 hi = rhc + max (ic, (4 t sdclk )) : read to write from same or different bank hi = rhc + (3 t sdclk ): read to read from same bank hi = rhc + max(ic, (3 t sdclk )) : read to read from different bank ic = (number of idle cycles sp ecified in amictlx register) t sdclk h = (number of hold cycles specified in amictlx register) t sdclk 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ms x, is referenced. 3 note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hdrh in asynchronous access mode. see test conditions on page 54 for the calculation of hold time s given capacitive and dc loads. 5 ami_ack delay/setup: user must meet t daak , or t dsak , for deassertion of ami_ack (low).
rev. 0 | page 32 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 figure 19. ami read ami_ack ami_data t drha t rw t hdrh t rwr t dad t darl t drld t sds t dsak t daak ami_wr ami_rd ami_addr ami_msx
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 33 of 68 | december 2010 ami write use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 33. ami write parameter min max unit timing requirements t daak 1, 2 ami_ack delay from address, selects t sdclk C 9.7 + w ns t dsak 1, 3 ami_ack delay from ami_wr low w C 6 ns switching characteristics t dawh 2 address selects to ami_wr deasserted t sdclk C3.1+ w ns t dawl 2 address selects to ami_wr low t sdclk C3 ns t ww ami_wr pulse width w C 1.3 ns t ddwh data setup before ami_wr high t sdclk C3.7+ w ns t dwha address hold after ami_wr deasserted h + 0.15 ns t dwhd data hold after ami_wr deasserted h ns t datrwh 4 data disable after ami_wr deasserted t sdclk C 4.3 + h t sdclk + 4.9 + h ns t wwr 5 ami_wr high to ami_wr low t sdclk C1.5+ h ns t ddwr data disable before ami_rd low 2 t sdclk C 6 ns t wde ami_wr low to data enabled t sdclk C 3.7 ns w = (number of wait states specified in amictlx register) t sdclk h = (number of hold cycles specified in amictlx register) t sdclk 1 ami_ack delay/setup: system must meet t daak , or t dsak , for deassertion of ami_ack (low). 2 the falling edge of msx is referenced. 3 note that timing for ami_ack, ami_rd , ami_wr , and strobe timing parameters only applies to asynchronous access mode. 4 see test conditions on page 54 for calculation of hold times given capacitive and dc loads. 5 for write to write: t sdclk + h, for both same bank and diff erent bank. for write to read: 3 t sdclk + h, for the same bank and different banks. figure 20. ami write ami_ack ami_data t dawh t dwha t wwr t datrwh t dwhd t ww t ddwr t ddwh t dawl t wde t dsak t daak ami_rd ami_wr ami_addr ami_msx
rev. 0 | page 34 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 serial ports in slave transmitter mode and master receiver mode, the maxi- mum serial port frequency is f pclk /8. in master transmitter mode and slave receiver mode, the maximum serial port clock frequency is f pclk /4. to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) sclk width. serial port signals (sclk, frame sync, data channel a, data channel b) are routed to the dai_p20C1 pins using the sru. therefore, the timing specificatio ns provided below are valid at the dai_p20C1 pins. table 34. serial portsexternal clock parameter min max unit timing requirements t sfse 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t hfse 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 1.9 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width (t pclk 4) 2 C 0.5 ns t sclk sclk period t pclk 4 ns switching characteristics t dfse 2 frame sync delay after sclk (internally generated frame sync in either transmit or receive mode) 10.25 ns t hofse 2 frame sync hold after sclk (internally generated frame sync in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 9 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 35. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 7 ns t hfsi 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 frame sync delay after sclk (internally generated frame sync in transmit mode) 4 ns t hofsi 2 frame sync hold after sclk (internally generated frame sync in transmit mode) C1 ns t dfsir 2 frame sync delay after sclk (internally generated frame sync in receive mode) 9.75 ns t hofsir 2 frame sync hold after sclk (internally generated frame sync in receive mode) C1 ns t ddti 2 transmit data delay after sclk 3.25 ns t hdti 2 transmit data hold after sclk C2 ns t sckliw transmit or receive sclk width 2 t pclk C 1.5 2 t pclk + 1.5 ns 1 referenced to the sample edge. 2 referenced to drive edge.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 35 of 68 | december 2010 figure 21. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw
rev. 0 | page 36 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 table 36. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external tr ansmit frame sync or external receive frame sync with mce = 1, mfd = 0 8.5 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justi fied, as well as dsp serial mode, and mce = 1, mfd = 0. figure 22. external late frame sync 1 1 this figure reflects changes made to support left -justified mode. drive sample external receive fs with mce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t t ddtenfs t sfse/i t hfse/i t hfse/i
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 37 of 68 | december 2010 table 37. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 11.5 ns t ddtin 1 data enable from internal transmit sclk C1.5 ns 1 referenced to drive edge. figure 23. serial portsenable and three-state drive edge drive edge drive edge t ddtin t ddten t ddtte dai_p20C1 (sclk, int) dai_p20C1 (data channel a/b) dai_p20C1 (sclk, ext) dai_p20C1 (data channel a/b)
rev. 0 | page 38 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 the sportx_tdv_o output sign al (routing unit) becomes active in sport multichannel mode. during transmit slots (enabled with active channe l selection registers) the sportx_tdv_o is asserted for communication with external devices. table 38. serial portstdm transmit data valid parameter min max unit switching characteristics 1 t drdven data-valid enable delay from drive edge of external clock 3 ns t dfdven data-valid disable delay from drive edge of external clock 8 ns t drdvin data-valid enable delay from drive edge of internal clock C1 ns t dfdvin data-valid disable delay from drive edge of internal clock 2 ns 1 referenced to drive edge. figure 24. serial portstdm internal and external clock drive edge drive edge dai_p20C1 (sclk, ext) t drdven t dfdven drive edge drive edge dai_p20C1 (sclk, int) t drdvin t dfdvin tdvx dai_p20-1 tdvx dai_p20-1
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 39 of 68 | december 2010 input data port (idp) the timing requirements for the idp are given in table 34 . idp signals are routed to the dai_p20C1 pins using the sru. there- fore, the timing specifications provided below are valid at the dai_p20C1 pins. table 39. input data port (idp) parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3.8 ns t sihfs 1 frame sync hold after serial clock rising edge 2.5 ns t sisd 1 data setup before serial clock rising edge 2.5 ns t sihd 1 data hold after serial clock rising edge 2.5 ns t idpclkw clock width (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 25. idp master timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t ipdclk t ipdclkw t sisfs t sihfs t sihd t sisd
rev. 0 | page 40 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 35 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the pdap, see the pdap chapter of the adsp-214xx sharc pr ocessor hardware reference . note that the 20 bits of external pdap data can be provided through the addr23C4 pins or over the dai pins. table 40. parallel data acquisition port (pdap) parameter min max unit timing requirements t sphold 1 pdap_hold setup before pdap_clk sample edge 2.5 ns t hphold 1 pdap_hold hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after pdap_clk sample edge 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1.5 ns 1 source pins of pdap_data are addr23C4 or dai pins. source pins for pdap_clk and pdap_hold are 1) dai pins; 2) clkin through pc g; 3) dai pins through pcg; or 4) addr3C2 pins. figure 26. pdap timing dai_p20C1 (pdap_clk) sample edge dai_p20C1 (pdap_hold) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t sphold t hphold t pdclk t pdclkw dai_p20C1/ addr23C4 (pdap_data)
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 41 of 68 | december 2010 sample rate converterserial input port the asrc input signals are rout ed from the dai_p20C1 pins using the sru. therefore, the timi ng specifications provided in table 41 are valid at the dai_p20C1 pins. table 41. asrc, serial input port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcsd 1 data setup before serial clock rising edge 4 ns t srchd 1 data hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 27. asrc serial input port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srchd t srcsd
rev. 0 | page 42 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 sample rate converterserial output port for the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to sclk on the output port. the serial data ou tput has a hold time and delay specification with regard to serial clock. note that serial clock rising edge is the sampling edge, and the falling edge is the drive edge. table 42. asrc, serial output port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns switching characteristics t srctdd 1 transmit data delay after serial clock falling edge 9.9 ns t srctdh 1 transmit data hold after serial clock falling edge 1 ns 1 the serial clock, data, and frame sync signals can come from an y of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. asrc serial output port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srctdd t srctdh
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 43 of 68 | december 2010 pulse-width modulation generators (pwm) the following timing specifications apply when the addr23C8/dpi_14C1 pins are configured as pwm. table 43. pulse-width modulation (pwm) timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 29. pwm timing pwm outputs t pwmw t pwmp
rev. 0 | page 44 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the following se ctions provide timing for the transmitter. s/pdif transmitter-serial input waveforms figure 30 shows the right-justified mo de. frame sync is high for the left channel and low for the ri ght channel. data is valid on the rising edge of serial clock. the msb is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period , the lsb of the data is right- justified to the next frame sync transition. table 44. s/pdif transmitter right-justified mode parameter nominal unit timing requirement t rjd frame sync to msb delay in right-justified mode 16-bit word mode 18-bit word mode 20-bit word mode 24-bit word mode 16 14 12 8 sclk sclk sclk sclk figure 30. right-justified mode msb left/right channel lsb lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t rjd
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 45 of 68 | december 2010 figure 31 shows the default i 2 s-justified mode. the frame sync is low for the left channel and hi for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition but with a delay. figure 32 shows the left-justified mo de. the frame sync is high for the left channel and low for th e right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition with no delay. table 45. s/pdif transmitter i 2 s mode parameter nominal unit timing requirement t i2sd frame sync to msb delay in i 2 s mode 1 sclk figure 31. i 2 s-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t i2sd table 46. s/pdif transmitter left-justified mode parameter nominal unit timing requirement t ljd frame sync to msb delay in left-justified mode 0 sclk figure 32. left-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t ljd
rev. 0 | page 46 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 s/pdif transmitter input data timing the timing requirements for th e s/pdif transmitter are given in table 47 . input signals are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics the s/pdif transmitter requires an oversampling clock input. this high frequency clock (txclk) input is divided down to generate the internal biphase clock. table 47. s/pdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3 ns t sihfs 1 frame sync hold after serial clock rising edge 3 ns t sisd 1 data setup before serial clock rising edge 3 ns t sihd 1 data hold after serial clock rising edge 3 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns t sisclkw clock width 36 ns t sisclk clock period 80 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 33. s/pdif transmitter input timing sample edge dai_p20C1 (txclk) dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (sdata) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sihfs t sisd t sihd table 48. oversampling clock (txc lk) switching characteristics parameter max unit frequency for txclk = 384 frame sync o versampling ratio frame sync <= 1/t sitxclk mhz frequency for txclk = 256 frame sync 49.2 mhz frame rate (fs) 192.0 khz
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 47 of 68 | december 2010 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 49. s/pdif receiver inte rnal digital pll mode timing parameter min max unit switching characteristics t dfsi frame sync delay after serial clock 5 ns t hofsi frame sync hold after serial clock C2 ns t ddti transmit data delay after serial clock 5 ns t hdti transmit data hold after serial clock C2 ns t sclkiw 1 transmit serial clock width 8 t pclk C 2 ns 1 sclk frequency is 64 fs where fs = the frequency of frame sync. figure 34. s/pdif receiver internal digital pll mode timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (data channel a/b) drive edge t sclkiw t dfsi t hofsi t ddti t hdti
rev. 0 | page 48 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 spi interfacemaster the adsp-2148x contains two spi ports. both pr imary and sec- ondary are available through dpi only. the timing provided in table 50 and table 51 applies to both. table 50. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 ns t sdscim dpi pin (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to dpi pin (spi device select) high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1.2 ns figure 35. spi master timing t spichm t sdscim t spiclm t spiclkm t hdsm t spitdm t ddspidm t hspidm t sspidm dpi (output) mosi (output) miso (input) mosi (output) miso (input) cphase = 1 cphase = 0 t hdspidm t hspidm t hspidm t sspidm t sspidm t ddspidm t hdspidm spiclk (cp = 0, cp = 1) (output)
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 49 of 68 | december 2010 spi interfaceslave table 51. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input set-up time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase=0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 7.5 ns t dsoe 1 spids assertion to data out active (spi2) 0 7.5 ns t dsdhi spids deassertion to data high impedance 0 10.5 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 10.5 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns 1 the timing for these parameters applies when the spi is routed through the signal ro uting unit. for more information, see the p rocessor hardware refere nce, serial peripheral interface port chapter. figure 36. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids t sspids t dsdhi t ddspids t dsov t hspids t sspids t hdspids spids (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0 spiclk (cp = 0, cp = 1) (input)
rev. 0 | page 50 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 media local bus all the numbers given are appl icable for all speed modes (1024 fs, 512 fs and 256 fs for 3- pin; 512 fs and 256 fs for 5-pin), unless otherwise specified. please refer to the medialb specification document revision 3.0 for more details. table 52. mlb interface, 3-pin specifications parameter min typ max unit 3-pin characteristics t mlbclk mlb clock period 1024 fs 512 fs 256 fs 20.3 40 81 ns ns ns t mckl mlbclk low time 1024 fs 512 fs 256 fs 6.1 14 30 ns ns ns t mckh mlbclk high time 1024 fs 512 fs 256 fs 9.3 14 30 ns ns ns t mckr mlbclk rise time (v il to v ih ) 1024 fs 512 fs/256 fs 1 3 ns ns t mckf mlbclk fall time (v ih to v il ) 1024 fs 512 fs/256 fs 1 3 ns ns t mpwv 1 mlbclk pulse width variation 1024 fs 512 fs/256 0.7 2.0 nspp nspp t dsmcf dat/sig input setup time 1 ns t dhmcf dat/sig input hold time 2 ns t mcfdz dat/sig output time to three-state 0 15 ns t mcdrv dat/sig output data delay from mlbclk rising edge 8 ns t mdzh 2 bus hold time 1024 fs 512 fs/256 2 4 ns ns c mlb dat/sig pin load 1024 fs 512 fs/256 40 60 pf pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns peak -to-peak (pp). 2 the board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for thi s time period. therefore, coupling must be minimized while meeting the ma ximum capacitive load listed.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 51 of 68 | december 2010 figure 37. mlb timing (3-pin interface) table 53. mlb interface, 5-pin specifications parameter min typ max unit 5-pin characteristics t mlbclk mlb clock period 512 fs 256 fs 40 81 ns ns t mckl mlbclk low time 512 fs 256 fs 15 30 ns ns t mckh mlbclk high time 512 fs 256 fs 15 30 ns ns t mckr mlbclk rise time (v il to v ih )6 n s t mckf mlbclk fall time (v ih to v il )6 n s t mpwv 1 mlbclk pulse width variation 2 nspp t dsmcf 2 dat/sig input setup time 3 ns t dhmcf dat/sig input hold time 5 ns t mcdrv ds/do output data delay from mlbclk rising edge 8 ns t mcrdl 3 do/so low from mlbclk high 512 fs 256 fs 10 20 ns ns c mlb ds/do pin load 40 pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns peak -to-peak (pp). 2 gate delays due to or'ing logic on the pins must be accounted for. 3 when a node is not driving valid data onto the bus, the mlbso and mlbdo output lines shall remain low. if the output lines can float at anytime, incl uding while in reset, external pull-down resistors are required to keep the outputs fr om corrupting the medialb signal lines when not being driven. t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbsig/ mlbdat (tx, output) t mcfdz t dsmcf mlbclk t mlbclk valid t dhmcf t mckf t mcdrv valid t mdzh
rev. 0 | page 52 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-214xx sharc hardware reference manual . 2-wire interface (twi)receive and transmit timing for information on the twi receive and transmit operations, see the adsp-214xx sharc hardwa re reference manual . figure 38. mlb timing (5-pin interface) figure 39. mlb 3-pin and 5-pin mlbc lk pulse width variation timing t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbso/ mlbdo (tx, output) t mcrdl t dsmcf mlbclk t mlbclk valid valid t dhmcf t mckf t mcdrv t mpwv t mpwv mlbclk
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 53 of 68 | december 2010 jtag test access port and emulation table 54. jtag test access port and emulation parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 1 system inputs = data15C0, clk_cfg1C0, reset , boot_cfg2C0, dai_px, dpi_px, and flag3C0. system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 10 ns t dsys 2 2 system outputs = dai_px, dpi_px addr23C0, ami_rd , ami_wr , flag3C0, sdras , sdcas , sdwe , sdcke, sda10, sddqm, sdclk and emu . system outputs delay after tck low t ck 2 + 7 ns figure 40. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. 0 | page 54 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 output drive currents figure 41 shows typical i-v characteri stics for the output driv- ers of the adsp-2148x, and table 55 shows the pins associated with each driver. the curves re present the current drive capabil- ity of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 21 on page 24 through table 54 on page 53 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 42 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 43 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 42 ). figure 46 and figure 47 show graphically how output delays an d holds vary with load capaci- tance. the graphs of figure 44 through figure 47 may not be linear outside the ranges show n for typical output delay vs. load capacitance and typical ou tput rise time (20% to 80%, v = min) vs. load capacitance. table 55. driver types driver type associated pins a flag[0C3], ami_addr[0C23], data[0C15], ami_rd , ami_wr , ami_ack, ms[1-0] , sdras , sdcas , sdwe , sddqm, sdcke, sda10, emu , tdo, resetout , dpi[1C14], dai[1C20], wdtrsto , mlbdat, mlbsig, mlbso, mlbdo, mlbclk bs d c l k figure 41. typical drive at junction temperature figure 43. voltage reference levels for ac measurements sweep (v ddext ) voltage (v) 0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 source/sink (v ddext ) current (ma) 150 50 - 100 - 200 - 150 - 50 v oh 3.13 v, 125 c v ol 3.13 v, 125 c type a type a type b type b input or output 1.5v 1.5v figure 42. equivalent device loading for ac measurements (includes all fixtures) figure 44. typical output rise/fall time (20% to 80%, v dd_ext = max) t1 zo = 50(impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to reflect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 load capacitance (pf) 6 0 0 7 4 2 1 3 rise and fall times (ns) 125 200 100 25 175 50 75 150 5 y = 0.0341x + 0.3093 y = 0.0153x + 0.2131 y = 0.0414x + 0.2661 y = 0.0152x + 0.1882 type a drive fall type a drive rise type b drive fall type b drive rise
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 55 of 68 | december 2010 thermal characteristics the adsp-2148x processor is ra ted for performance over the temperature range specified in operating conditions on page 17 . table 57 airflow measurements comply with jedec standards jesd51-2 and jesd51-6, and th e junction-to-board measure- ment complies with jesd51-8. test board design complies with jedec standards jesd51-7 (lqfp_ ep). the junction-to-case measurement complies with mi l- std-883. all measurements use a 2s2p jedec test board. to determine the junction temper ature of the device while on the application pcb, use: where: t j = junction temperature c t case = case temperature (c) measured at the top center of the package ? jt = junction-to-top (of package) characterization parameter is the typical value from table 57 . p d = power dissipation values of ? ja are provided for package comparison and pcb design considerations. ? ja can be used for a first order approxi- mation of t j by the equation: where: t a = ambient temperature c values of ? jc are provided for pack age comparison and pcb design considerations when an external heatsink is required. figure 45. typical outp ut rise/fall time (20% to 80%, v dd_ext = min) figure 46. typical output rise/fall delay (v dd_ext = max) load capacitance (pf) 6 0 0 10 4 2 rise and fall times (ns) 25 200 150 50 75 100 125 175 y = 0.0571x + 0.5558 y = 0.0278x + 0.3138 y = 0.0258x + 0.3684 type a drive fall type a drive rise type b drive rise type b drive fall 8 12 14 y = 0.0747x + 0.5154 load capacitance (pf) 3 0 3.5 2 1 0.5 1.5 rise and fall delay (ns) 2.5 y = 0.0152x + 1.7607 y = 0.0068x + 1.7614 y = 0.0196x + 1.2945 y = 0.0074x + 1.421 0 25 200 150 50 75 100 125 175 type a drive fall type a drive rise type b drive rise type b drive fall 4 4.5 figure 47. typical ou tput rise/fall delay (v dd_ext = min) load capacitance (pf) 6 0 0 7 4 2 1 3 rise and fall times delay (ns) 125 200 100 25 175 50 75 150 5 y = 0.0256x + 3.5859 y = 0.0116x + 3.5697 8 y = 0.0359x + 2.924 9 y = 0.0136x + 3.1135 type a drive fall type a drive rise type b drive fall type b drive rise t j t case ? jt p d ? ?? += t j t a ? ja p d ? ?? +=
rev. 0 | page 56 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 values of ? jb are provided for package comparison and pcb design considerations. note that the thermal characteristics val- ues provided in table 56 and table 57 are modeled values. thermal diode the adsp-2148x processors incorporate thermal diode/s to monitor the die temperature. the thermal diode of is a grounded collector, pnp bipolar ju nction transistor (bjt). the thd_p pin is connected to the emitter and the thd_m pin is connected to the base of the tran sistor. these pins can be used by an external temperature sensor (such as adm 1021a or lm86 or others) to read the die temperature of the chip. the technique used by the extern al temperature sensor is to measure the change in vbe when the thermal diode is operated at two different currents. this is shown in the following equation: where: n = multiplication factor clos e to 1, depending on process variations k = boltzmanns constant t = temperature (c) q = charge of the electron n = ratio of the two currents the two currents are usually in the range of 10 micro amperes to 300 micro amperes for the common temperature sensor chips available. table 58 contains the thermal diod e specifications using the transistor model. table 56. thermal characteristics for 100-lead lqfp_ep parameter condition typical unit ? ja airflow = 0 m/s 17.8 c/w ? jma airflow = 1 m/s 15.4 c/w ? jma airflow = 2 m/s 14.6 c/w ? jc 2.4 c/w ? jt airflow = 0 m/s 0.24 c/w ? jmt airflow = 1 m/s 0.37 c/w ? jmt airflow = 2 m/s 0.51 c/w table 57. thermal characteristics for 176-lead lqfp_ep parameter condition typical unit ? ja airflow = 0 m/s 16.9 c/w ? jma airflow = 1 m/s 14.6 c/w ? jma airflow = 2 m/s 13.8 c/w ? jc 2.3 c/w ? jt airflow = 0 m/s 0.21 c/w ? jmt airflow = 1 m/s 0.32 c/w ? jmt airflow = 2 m/s 0.41 c/w ? v be n kt q ------ in(n) ?? = table 58. thermal diode parameters C transistor model 1 symbol parameter min typ max unit i fw 2 forward bias current 10 300 a i e emitter current 10 300 a n q 3, 4 transistor ideality 1.012 1.015 1.017 r t 3, 5 series resistance 0.12 0.2 0.28 1 see engineer-to-engineer note ee-346. 2 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 3 specified by design characterization. 4 the ideality factor, nq, represents the deviation from ideal diode behavior as exem plified by the diode equation: i c = i s (e qvbe/nqkt C1) where i s = saturation current, q = electronic charge, v be = voltage across the diode, k = boltzmann co nstant, and t = absolute temperature (kelvin). 5 the series resistance (r t ) can be used for more ac curate readings as needed.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 57 of 68 | december 2010 100-lqfp_ep lead assignment table 59. 100-lead lqfp_ep lead assign ments (numerical by lead number) lead name lead no. lead name lead no. lead name lead no. lead name lead no. v dd_int 1v dd_ext 26 dai_p10 51 v dd_int 76 clk_cfg1 2 dpi_p08 27 v dd_int 52 flag0 77 boot_cfg0 3 dpi_p07 28 v dd_ext 53 v dd_int 78 v dd_ext 4v dd_int 29 dai_p20 54 v dd_int 79 v dd_int 5 dpi_p09 30 v dd_int 55 flag1 80 boot_cfg1 6 dpi_p10 31 dai_p08 56 flag2 81 gnd 7 dpi_p11 32 dai_p04 57 flag3 82 nc 8 dpi_p12 33 dai_p14 58 mlbclk 83 nc 9 dpi_p13 34 dai_p18 59 mlbdat 84 clk_cfg0 10 dai_p03 35 dai_p17 60 mlbdo 85 v dd_int 11 dpi_p14 36 dai_p16 61 v dd_ext 86 clkin 12 v dd_int 37 dai_p15 62 mlbsig 87 xtal 13 v dd_int 38 dai_p12 63 v dd_int 88 v dd_ext 14 v dd_int 39 v dd_int 64 mlbso 89 v dd_int 15 dai_p13 40 dai_p11 65 trst 90 v dd_int 16 dai_p07 41 v dd_int 66 emu 91 resetout /runrstin 17 dai_p19 42 v dd_int 67 tdo 92 v dd_int 18 dai_p01 43 gnd 68 v dd_ext 93 dpi_p01 19 dai_p02 44 thd_m 69 v dd_int 94 dpi_p02 20 v dd_int 45 thd_p 70 tdi 95 dpi_p03 21 v dd_ext 46 v dd_thd 71 tck 96 v dd_int 22 v dd_int 47 v dd_int 72 v dd_int 97 dpi_p05 23 dai_p06 48 v dd_int 73 reset 98 dpi_p04 24 dai_p05 49 v dd_int 74 tms 99 dpi_p06 25 dai_p09 50 v dd_int 75 v dd_int 100 gnd 101* mlb pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. for no n-automotive models, these pins should b e connected to ground (gnd). * pin no. 101 is the gnd supply (see figure 48 and figure 49 ) for the processor; this pad must be robustly connected to gnd.
rev. 0 | page 58 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 figure 48 shows the top view of the 100-lead lqfp_ep lead configuration. figure 49 shows the bottom vi ew of the 100-lead lqfp_ep lead configuration. figure 48. 100-lead lqfp_ep lead configuration (top view) lead 1 lead 25 lead 75 lead 51 lead 100 lead 76 lead 26 lead 50 lead 1 indicator ad s p-214 8 x 100-lead lqfp_ep top view figure 49. 100-lead lqfp_ep lead configuration (bottom view) lead 75 lead 51 lead 1 lead 25 lead 76 lead 100 lead 50 lead 26 lead 1 indicator gnd pad (lead 101) ad s p-214 8 x 100-lead lqfp_ep bottom view
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 59 of 68 | december 2010 176-lead lqfp_ep lead assignment table 60. adsp-21486 176-lead lqfp_ep lead as signment (numerical by lead number) lead name lead no. lead name lead no. lead name lead no. lead name lead no. nc 1 v dd_ext 45 dai_p10 89 v dd_int 133 ms0 2dpi_p08 46v dd_int 90 flag0 134 nc 3 dpi_p07 47 v dd_ext 91 flag1 135 v dd_int 4v dd_int 48 dai_p20 92 flag2 136 clk_cfg1 5 dpi_p09 49 v dd_int 93 gnd 137 addr0 6 dpi_p10 50 dai_p08 94 flag3 138 boot_cfg0 7 dpi_p11 51 dai_p14 95 gnd 139 v dd_ext 8 dpi_p12 52 dai_p04 96 gnd 140 addr1 9 dpi_p13 53 dai_p18 97 v dd_ext 141 addr2 10 dpi_p14 54 dai_p17 98 gnd 142 addr3 11 dai_p03 55 dai_p16 99 v dd_int 143 addr4 12 nc 56 dai_p12 100 trst 144 addr5 13 v dd_ext 57 dai_p15 101 gnd 145 boot_cfg1 14 nc 58 v dd_int 102 emu 146 gnd 15 nc 59 dai_p11 103 data0 147 addr6 16 nc 60 v dd_ext 104 data1 148 addr7 17 nc 61 v dd_int 105 data2 149 nc 18 v dd_int 62 boot_cfg2 106 data3 150 nc 19 nc 63 v dd_int 107 tdo 151 addr8 20 nc 64 ami_ack 108 data4 152 addr9 21 v dd_int 65 gnd 109 v dd_ext 153 clk_cfg0 22 nc 66 thd_m 110 data5 154 v dd_int 23 nc 67 thd_p 111 data6 155 clkin 24 v dd_int 68 v dd_thd 112 v dd_int 156 xtal 25 nc 69 v dd_int 113 data7 157 addr10 26 wdtrsto 70 v dd_int 114 tdi 158 nc 27 nc 71 ms1 115 nc 159* v dd_ext 28 v dd_ext 72 v dd_int 116 v dd_ext 160 v dd_int 29 dai_p07 73 wdt_clko 117 data8 161 addr11 30 dai_p13 74 wdt_clkin 118 data9 162 addr12 31 dai_p19 75 v dd_ext 119 data10 163 addr17 32 dai_p01 76 addr23 120 tck 164 addr13 33 dai_p02 77 addr22 121 data11 165 v dd_int 34 v dd_int 78 addr21 122 data12 166 addr18 35 nc 79 v dd_int 123 data14 167 resetout /runrstin 36 nc 80 addr20 124 data13 168 v dd_int 37 nc 81 addr19 125 v dd_int 169 dpi_p01 38 nc 82 v dd_ext 126 data15 170 dpi_p02 39 nc 83 addr16 127 nc 171 dpi_p03 40 v dd_ext 84 addr15 128 nc 172 v dd_int 41 v dd_int 85 v dd_int 129 reset 173 dpi_p05 42 dai_p06 86 addr14 130 tms 174 dpi_p04 43 dai_p05 87 ami_wr 131 nc 175 dpi_p06 44 dai_p09 88 ami_rd 132 v dd_int 176 gnd 177** *no external connection should be made to this pin. use as nc only. ** lead no. 177 is the gnd supply (see figure 50 and figure 51 ) for the processor; this pad must be robustly connected to gnd.
rev. 0 | page 60 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 table 61. adsp-21483, adsp-21487, adsp-21488, and ad sp-21489 176-lead lqfp_ep lead assignment (numerical by lead number) lead name lead no. lead name lead no. lead name lead no. lead name lead no. sddqm 1 v dd_ext 45 dai_p10 89 v dd_int 133 ms0 2dpi_p08 46v dd_int 90 flag0 134 sdcke 3 dpi_p07 47 v dd_ext 91 flag1 135 v dd_int 4v dd_int 48 dai_p20 92 flag2 136 clk_cfg1 5 dpi_p09 49 v dd_int 93 gnd 137 addr0 6 dpi_p10 50 dai_p08 94 flag3 138 boot_cfg0 7 dpi_p11 51 dai_p14 95 gnd 139 v dd_ext 8 dpi_p12 52 dai_p04 96 gnd 140 addr1 9 dpi_p13 53 dai_p18 97 v dd_ext 141 addr2 10 dpi_p14 54 dai_p17 98 gnd 142 addr3 11 dai_p03 55 dai_p16 99 v dd_int 143 addr4 12 nc 56 dai_p12 100 trst 144 addr5 13 v dd_ext 57 dai_p15 101 gnd 145 boot_cfg1 14 nc 58 v dd_int 102 emu 146 gnd 15 nc 59 dai_p11 103 data0 147 addr6 16 nc 60 v dd_ext 104 data1 148 addr7 17 nc 61 v dd_int 105 data2 149 nc 18 v dd_int 62 boot_cfg2 106 data3 150 nc 19 nc 63 v dd_int 107 tdo 151 addr8 20 nc 64 ami_ack 108 data4 152 addr9 21 v dd_int 65 gnd 109 v dd_ext 153 clk_cfg0 22 nc 66 thd_m 110 data5 154 v dd_int 23 nc 67 thd_p 111 data6 155 clkin 24 v dd_int 68 v dd_thd 112 v dd_int 156 xtal 25 nc 69 v dd_int 113 data7 157 addr10 26 wdtrsto 70 v dd_int 114 tdi 158 sda10 27 nc 71 ms1 115 sdclk 159 v dd_ext 28 v dd_ext 72 v dd_int 116 v dd_ext 160 v dd_int 29 dai_p07 73 wdt_clko 117 data8 161 addr11 30 dai_p13 74 wdt_clkin 118 data9 162 addr12 31 dai_p19 75 v dd_ext 119 data10 163 addr17 32 dai_p01 76 addr23 120 tck 164 addr13 33 dai_p02 77 addr22 121 data11 165 v dd_int 34 v dd_int 78 addr21 122 data12 166 addr18 35 nc 79 v dd_int 123 data14 167 resetout /runrstin 36 nc 80 addr20 124 data13 168 v dd_int 37 nc 81 addr19 125 v dd_int 169 dpi_p01 38 nc 82 v dd_ext 126 data15 170 dpi_p02 39 nc 83 addr16 127 sdwe 171 dpi_p03 40 v dd_ext 84 addr15 128 sdras 172 v dd_int 41 v dd_int 85 v dd_int 129 reset 173 dpi_p05 42 dai_p06 86 addr14 130 tms 174 dpi_p04 43 dai_p05 87 ami_wr 131 sdcas 175 dpi_p06 44 dai_p09 88 ami_rd 132 v dd_int 176 gnd 177* * lead no. 177 is the gnd supply (see figure 50 and figure 51 ) for the processor; this pad must be robustly connected to gnd.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 61 of 68 | december 2010 figure 50 shows the top view of the 176-lead lqfp_ep lead configuration. figure 51 shows the bottom vi ew of the 176-lead lqfp_ep lead configuration. figure 50. 176-lead lqfp_ep lead configuration (top view) lead 1 lead 44 lead 1 3 2 lead 8 9 lead 176 lead 1 33 lead 45 lead 88 lead 1 indicator ad s p-214 8 x 176-lead lqfp_ep top view figure 51. 176-lead lqfp_ep lead configuration (bottom view) lead 1 3 2 lead 8 9 lead 1 lead 44 lead 1 33 lead 176 lead 88 lead 45 lead 1 indicator gnd pad (lead 177) ad s p-214 8 x 176-lead lqfp_ep bottom view
rev. 0 | page 62 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 outline dimensions the adsp-2148x processors ar e available in 100-lead and 176-lead lqfp_ep rohs compliant packages. figure 52. 100-lead low profile quad flat package, exposed pad [lqfp_ep] (sw-100-2) dimensions shown in millimeters compliant to jedec standards ms-026-bed-hd 0.08 coplanarity 1.45 1.40 1.35 0.20 0.15 0.09 0.15 0.10 0.05 7 3.5 0 view a rotated 90 ccw top view (pins down) bottom view (pins up) exposed pad 1 1 25 25 26 26 50 50 76 76 100 100 75 75 51 51 0.27 0.22 0.17 0.50 bsc lead pitch view a 1.60 max seating plane 0.75 0.60 0.45 pin 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 6.00 ref for proper connection of the exposed pad, refer to surface-mount design in this data sheet.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 63 of 68 | december 2010 surface-mount design the exposed pad is required to be electrically and thermally connected to gnd. implement this by soldering the exposed pad to a gnd pcb land that is the same size as the exposed pad. the gnd pcb land should be ro bustly connected to the gnd plane in the pcb for best electr ical and thermal performance. no separate gnd pins are provided in the package. figure 53. 176-lead low profile quad flat package, exposed pad [lqfp_ep] (sw-176-2) dimensions shown in millimeters compliant to jedec standards ms-026-bga-hd 0.15 0.10 0.05 0.08 coplanarity 0.20 0.15 0.09 1.45 1.40 1.35 7 3.5 0 view a rotated 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc lead pitch 24.10 24.00 sq 23.90 26.20 26.00 sq 25.80 top view (pins down) bottom view (pins up) exposed pad 1 44 1 44 45 89 88 45 88 132 89 132 176 133 176 133 pin 1 1.60 max 1.00 ref seating plane view a 6.00 ref 21.50 ref for proper connection of the exposed pad, refer to surface-mount design in this data sheet.
rev. 0 | page 64 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 automotive products the following models are availa ble with controlled manufactur- ing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. only the automotive grade products shown in table 62 are available for use in automotive applica- tions. contact your local adi acco unt representative for specific product ordering information and to obtain the specific auto- motive reliability reports for these models. table 62. automotive products model 1 temperature range 2 ram processor instruction rate (max) package description package option ad21488wbswz4xx C40c to +85c 3 mbit 400 mhz 100-lead lqfp_ep sw-100-2 AD21488WYSWZ4XX C40c to +105c 3 mbit 400 mhz 100-lead lqfp_ep sw-100-2 ad21489wbswz4xx C40c to +85c 5 mbit 400 mhz 100-lead lqfp_ep sw-100-2 1 z =rohs compliant part. 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 17 for junction temperature (t j ) specification which is the on ly temperature specification.
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 65 of 68 | december 2010 ordering guide model 1, 2 1 z = rohs compliant part. 2 the adsp-21488kswz-3a1 contains a C140 db sample rate converter. temperature range 3 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 17 for junction temperature (t j ) specification, which is the on ly temperature specification. ram processor instruction rate (max) package description package option adsp-21483kswz-2b 0c to +70c 3 mbit 300 mhz 176-lead lqfp_ep sw-176-2 adsp-21483kswz-3b 0c to +70c 3 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21483kswz-4b 0c to +70c 3 mbit 400 mhz 176-lead lqfp_ep sw-176-2 adsp-21486kswz-2a 0c to +70c 5 mbit 300 mhz 100-lead lqfp_ep sw-100-2 adsp-21486kswz-3a 0c to +70c 5 mbit 350 mhz 100-lead lqfp_ep sw-100-2 adsp-21486kswz-4a 0c to +70c 5 mbit 400 mhz 100-lead lqfp_ep sw-100-2 adsp-21486kswz-2b 0c to +70c 5 mbit 300 mhz 176-lead lqfp_ep sw-176-2 adsp-21486kswz-3b 0c to +70c 5 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21487kswz-2b 0c to +70c 5 mbit 300 mhz 176-lead lqfp_ep sw-176-2 adsp-21487kswz-3b 0c to +70c 5 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21487kswz-4b 0c to +70c 5 mbit 400 mhz 176-lead lqfp_ep sw-176-2 adsp-21488kswz-3a 0c to +70c 3 mbit 350 mhz 100-lead lqfp_ep sw-100-2 adsp-21488kswz-3a1 0c to +70c 3 mbit 350 mhz 100-lead lqfp_ep sw-100-2 adsp-21488kswz-4a 0c to +70c 3 mbit 400 mhz 100-lead lqfp_ep sw-100-2 adsp-21488bswz-4a C40c to +85c 3 mbit 400 mhz 100-lead lqfp_ep sw-100-2 adsp-21488kswz-3b 0c to +70c 3 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21488bswz-3b C40c to +85c 3 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21488kswz-4b 0c to +70c 3 mbit 400 mhz 176-lead lqfp_ep sw-176-2 adsp-21488bswz-4b C40c to +85c 3 mbit 400 mhz 176-lead lqfp_ep sw-176-2 adsp-21489kswz-3a 0c to +70c 5 mbit 350 mhz 100-lead lqfp_ep sw-100-2 adsp-21489bswz-3a C40c to +85c 5 mbit 350 mhz 100-lead lqfp_ep sw-100-2 adsp-21489kswz-4a 0c to +70c 5 mbit 400 mhz 100-lead lqfp_ep sw-100-2 adsp-21489bswz-4a C40c to +85c 5 mbit 400 mhz 100-lead lqfp_ep sw-100-2 adsp-21489kswz-3b 0c to +70c 5 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21489bswz-3b C40c to +85c 5 mbit 350 mhz 176-lead lqfp_ep sw-176-2 adsp-21489kswz-4b 0c to +70c 5 mbit 400 mhz 176-lead lqfp_ep sw-176-2 adsp-21489bswz-4b C40c to +85c 5 mbit 400 mhz 176-lead lqfp_ep sw-176-2
rev. 0 | page 66 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489
adsp-21483/adsp-21486/adsp-21487/adsp-21488/adsp-21489 rev. 0 | page 67 of 68 | december 2010
rev. 0 | page 68 of 68 | december 2010 adsp-21483/adsp-21486/adsp-2 1487/adsp-21488/adsp-21489 ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09018-0-12/10(0)

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